FPGA Communications Cores from Anchor Hill
January 4, 2012

Anchor Hill now has available for license an extensive library of FPGA cores for digital communications systems. The cores span the implementation range from complete high-speed single-carrier modulators and demodulators to component sub-blocks such as the following:

DDS/NCO
Digital Filters: decimating, polyphase, DAC correction, interpolating
Synchronization: Carrier PLL, Symbol timing PLL, FLL, frame synch
High-performance carrier phase detectors for QAM
Complex up and down conversion
Equalization
Mobile Phase Recovering Equalizer (MPRE)(Patent Pending)
Slicer (QPSK, 16-QAM, 32-QAM, 64-QAM)
SNR estimation
Bit Error Rate Tester (BERT)(Has components in both modulator and demodulator)
Noise Generator for Built-in-Self-Test (BIST)
PRBS Generators (multiple types and lengths)
Many other modulator and demodulator functions

Cores are deliverable as black-boxed netlists for Xilinx FPGA target platforms. Cores can be delivered individually or multiple cores may be integrated as required. Many of the cores are configurable, parameterized and customizable for specific applications. All cores are field-tested and proven in deployed commercial products.

Anchor Hill also provides Engineering services and support for application system analysis, architecture development, integration and testing using Anchor Hill-provided library components and cores. Custom development of specialty communication cores is also available.

We will be releasing product specification data sheets for various cores in the coming weeks, including the Mobile Phase Recovering Equalizer (MPRE), which provides mobile multipath capability to high-rate single-carrier systems.

For more information contact: .(JavaScript must be enabled to view this email address)

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